A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer, e.g., a silicon surface layer of a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Thus, physical characteristics of each individual FET in a circuit formed on the same chip of the same wafer depend, primarily, on these to shapes. In sensitive circuits that use matched or a balanced pair FETs such as sense amplifiers, relatively minor can erode signal margin, at best impairing performance. In critical logic paths such device variations can change signal arrival times, causing race conditions.
Each layer of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition and etc. Regular mask shapes may be grouped into one of four types: line/space arrays, isolated lines, isolated spaces, and contact holes. Ideally, fabrication parameters applied to features on a particular layer to affect all types of features uniformly on that layer. Unfortunately, all feature types do not respond uniformly, e.g., to focus. For example, minimum pitch lines may widen (and spaces shrink) out-of-focus, while isolated lines get narrower. This dichotomy has become especially troublesome as image dimensions and especially, FET gate lengths have shrunk.
Typically, each level includes targets at a number of chip locations or sites and subsequent levels are aligned to these targets. These targets normally include structures for focus and each layer is aligned to a previous layer. The tool is typically focused (through a layer of photoresist) on the particular structure in a previous layer as well. Focus may depend on a number of factors. The focus may vary within the field of focus, i.e., features at the edge of the field print (e.g., die or wafer) somewhat differently than features in the center. A typical wafer exhibits some across the wafer thickness difference, causing a difference in depth of focus across the wafer. Also, while nearly uniform, the photoresist layer thickness may be thicker/thinner at one point than others. Consequently, in-focus at the one point may be out-of-focus at others and vice-versa. Wear and tear on the stepping tool may result in site-to-site focus variations. Further, the variation may change and even become more pronounced as each layer is formed. Consequently, as features have shrunk, it has become increasingly difficult to control the Across Chip Linewidth Variation (ACLV).
So, since ACLV results in local as well as distributed gate length variations, designers are forced to increase design margins to compensate for/offset resulting variations. This is known as guard-banding and is normally effected with conservative device models to heavily guard-band a technology and add wide operating design margins. The effects of device variability on performance can be addressed/reduced with sophisticated statistical models to better describe the devices. Further, these effects can also addressed on a device by device basis by considering systematic device or circuit model variation. Regardless of the approach to address these variabilities, ACLV has increased data processing time to prepare guard-banded layouts in state of the art technologies for photo mask creation.
Thus, there is a need for reduced improved immunity to device layout sensitivity to focus variations.